The present invention generally relates to methods for fabricating a wafer structure having a strained silicon layer, and to an intermediate product for fabricating such a wafer structure.
Fabricating semiconductor structures that include a strained silicon layer are very interesting for microelectronic or optoelectronic applications since strained silicon layers have excellent electronic properties. The electronic properties include an increased carrier mobility that results in high efficiency electronic products. Conventional methods for fabricating structures with strained silicon layers are very complex and time-consuming. In particular, it is known to epitaxially grow a SiGe buffer layer on a silicon substrate, and such a buffer layer has a gradually increasing germanium content. The SiGe buffer layer is normally epitaxially grown over a relatively long period of time with only slight changes of germanium content, resulting in a portion on top of the SiGe layer having a very low dislocation density. Then, a relaxed SiGe layer having a constant germanium concentration corresponding to the highest germanium concentration of the SiGe buffer layer is formed on the SiGe buffer layer. A strained silicon layer is next formed thereon. The requirements for first achieving a high quality of strained silicon structures and second for achieving high production efficiency are at odds with each other, because time-consuming process steps are necessary to obtain high quality structures.
Another method for fabricating SGOI (silicon-germanium-on-insulator) structures includes using the SMART-CUT® process. In particular, a relaxed SiGe layer is formed on a silicon support substrate and is then detached. Thereafter, strained epitaxial silicon is formed on the detached SiGe layer. This technique for fabricating such SGOI layers is time consuming and complex since the formation of the SiGe layer must be repeated for each new wafer product. Thus, each new structure requires conducting at least two epitaxy processes.
There are several disadvantages associated with the above described technologies including the need to repeat complex processing steps, and the difficulty of recycling the original substrates from which a layer has been detached. Chemical mechanical polishing steps and/or chemical etching steps are used to bring the original substrate to a state in which it is reusable. Such recycling processes are used to reduce the surface roughness and to remove a step profile formed on the edge of the wafers, but also reduce the thickness of the original wafer. Such steps are also time-consuming. Moreover, it is difficult to use chemical etching since it is not selective enough to recognize the interface between a SiGe layer having a gradually changing composition and the silicon substrate. It is therefore necessary to apply a complementary chemical-mechanical polishing step, or to replace chemical etching with a chemical-mechanical polishing step. Chemical-mechanical polishing steps are not easily reproducible, and are somewhat inefficient.
International published application WO 2004 019 404 describes a method that utilizes protective layers such as stop layers to protect a layer that is located under a recycled layer during the recycling process. Although such stop layers are able to protect an SiGe buffer layer on a donor or support substrate, such a method cannot solve all the problems inherent in the prior art. In particular, the SiGe buffer layer has been subjected to multiple processing steps which form dislocations so that long-term epitaxial processes are necessary to form a new usable donor wafer, wherein the dislocation density is greatly reduced to form a good base to form a high-quality strained silicon layer.
In another approach, only a part of the relaxed SiGe layer is transferred onto another substrate and is further grown thereon to provide a good base for a strained silicon layer. This technique eliminates the need to form a buffer layer and thus results in increasing the efficiency of the process. The technique also eliminates the risk of a forming dislocations when fabricating the buffer layer. However, as mentioned above, performing repeated SiGe epitaxy on the transferred SiGe layer is difficult to control which leads to inefficiency. For instance, pre-treating the surface of SiGe layers before epitaxially depositing SiGe is typically more difficult than depositing a strained Si layer.